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1.5-4

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AS3643

Datasheet, Confidential - E l e c t r i c a l C h a r a c t e r i s t i c s

LOW Period of SCL

Clock

1.3

µs

HIGH Period of SCL

Clock

0.6

µs

Setup Time for a

Repeated START

Condition

0.6

µs

Data Hold Time

7

00.9

µs

Data Setup Time

8

100

ns

Rise Time of Both

SDA and SCL Signals

20 +

300

ns

Fall Time of Both SDA

and SCL Signals

20 +

300

ns

Setup Time for STOP

Condition

0.6

µs

Capacitive Load for

Each Bus Line

400

pF

I/O Capacitance

(SDA, SCL)

10

pF

2. To improve efficiency at low output currents, the active part of the internal switching transistor PMOS is reduced

in size to 1/5 its original size. This reduces the current required to drive the PMOS transistor and therefore

improves overall efficiency at low output currents.

5. A pulldown current of 36µA is equal to a pulldown resistor of 42k

 at 1.5V

6. After this period, the first clock pulse is generated.

SCL signal) to bridge the undefined region of the falling edge of SCL.

be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

Table 4. Electrical Characteristics (Continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit