SPECIFICA TIONS

(Typical @ +25ºC and rated power supply unless otherwise noted)

SERIES

HS A DC85

POW ER SUPPLY

Requirements

+15V , Rated

+14.25 to +15.75V @ 28 mA (max)

–15V , Rated

–14.25V to+15.75V @ 30 mA (max)

+5V , Rated

+4.75V to +5.25V @ 91 mA (max)

Rejection Ratio

+15V Supply

±0.005% F.S.R,/% V s

–15V Supply

±0.005% F.S.R,/% V s

+5V Supply

±0.002% F.S.R,/% V s

Power Consumption

1.32W (max)

TEM PERA TURE

Operating

–55ºC to +125ºC B V ersion

ºC to 70ºC

C V ersion

M ECHA NICA L

Case Style

32-Pin Hermetic M etal

NOTES

1. For 20V step to 0.01% . Settling Time adds to Conversion Time when buffer is connected to input.

2. DTL/TTL compatible, i.e. logic “ 0” = 0.8V max. logic “ 1” = 2.0V min., for inputs and. for digital outputs, logic “ 0” = +0.4V max. and logic “ 1” = 2.4V min.

3. See TIM ING DIA GRA M under A PPLICA TIONS INFORM A TION.

4. HS A DC85 can accept external clock. See TIM ING DIA GRA M under A PPLICA TIONS INFORM A TION.

5. Externally adjustable, see OPTIONA L OFFSET A ND GA IN A DJUSTM ENTS under A PPLICA TIONS INFORM A TION.

CA SE ENV ELOPE DIM ENSIONS

1.150

(29.21)

M A X

0.900

(22.86)

0.220

(5.588)

M IN

0.018 ±0.002

(0.457 ±0.050)

0.220

(5.588)

M A X

1.750

(44.45)

M A X

0.100

(2.540)

TY P

0.10

(2.54)

TOP V IEW

RED DOT

INDICA TES PIN 1

DIM ENSIONS

INCHES

(M M )

0.10

(2.54)

1

32

16

17

PIN

FUNCTION

PIN

FUNCTION

1

BIT12(LSB)

32

SERIA L OUT

2

BIT 11

31

–15V

3

BIT 10

30

BUFFER IN

4

BIT 9

29

BUFFER OUT

5

BITS

28

+15V

6

BIT 7

27

GA IN A DJ.

7

BIT 6

26

A NA LOG GND.*

8

BIT 5

25

20V RA NGE

9

BIT 4

24

10V RA NGE

10

BIT 3

23

BIPOLA R OFFSET

11

BIT 2

22

COM PA RA TOR IN

12

BIT 1(M SB)

21

STA RT

13

BIT 1 (M SB)

20

STA TUS

14

SHORT CY CLE

19

CLOCK OUT

15

DIGITA L GND.

18

REF OUT

16

+5V

17CLOCK RA TE CONTROL* *

•

DIGITA L GND (Pin 15), and A NA LOG GND (Pin 26) should be tied

together as close to the unit as possible. If these grounds must be run

separately, use a wide conductor pattern and a nonpolarized 0.01 jiF to

0.1 p,F bypass capacitor between the two.

* * See A PPLICA TIONS INFORM A TION for connections.

PIN A SSIGNM ENTS

HS ADC85 SERIES