TTP-C2NF Communication Controller – Data Sheet

AS8202NF

Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.

10

Pin Name

Mode

Width

Comment

INTB

out (open drain)

1

CNI interrupt, time signal, active low

RAM_CLK_TESTSE

in

1

HOST clock

USE_RAM_CLK

in

1

HOST clock pin enable

Asynchronous READYB permits the shortest possible bus cycle but eventually requires signal

synchronization in the application. Connect USE_RAM_CLK to VSS to enable this mode of

operation.

Synchronous READYB uses an external clock (usually the host processor’s bus clock) for

synchronization of the signal eliminating external synchronization logic. Connect

USE_RAM_CLK to VDD and RAM_CLK_TESTSE to the host processor's bus clock to enable

this mode of operation.

Note: Due to possible metastability occurrence, it is not recommended to be used in safety critical systems.