5-291

FAST AND LS TTL DATA

SN54/74LS165

LOGIC DIAGRAM

PL

CP1

P4

P6

P5

P7

CP2

P3

P1

P2

P0

DS

PRESET

S

CP

R CL

Q0

Q0

PRESET

S

CP

R CL

Q1

Q1

PRESET

S

CP

R CL

Q2

Q2

PRESET

S

CP

R CL

Q3

Q3

PRESET

S

CP

R CL

Q4

Q4

PRESET

S

CP

R CL

Q5

Q5

PRESET

S

CP

R CL

Q6

Q6

PRESET

S

CP

R CL

Q7

Q7

14

1

2

6

3

4

5

11

12

10

13

15

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

7

9

FUNCTIONAL DESCRIPTION

The SN54/74LS165 contains eight clocked master/slave

RS flip-flops connected as a shift register, with auxiliary gating

to provide overriding asynchronous parallel entry. Parallel

data enters when the PL signal is LOW. The parallel data can

change while PL is LOW, provided that the recommended set-

up and hold times are observed.

For clock operation, PL must be HIGH. The two clock inputs

perform identically; one can be used as a clock inhibit by

applying a HIGH signal. To avoid double clocking, however,

the inhibit signal should only go HIGH while the clock is HIGH.

Otherwise, the rising inhibit signal will cause the same

response as a rising clock edge. The flip-flops are

edge-triggered for serial operations. The serial input data can

change at any time, provided only that the recommended

setup and hold times are observed, with respect to the rising

edge of the clock.

GUARANTEED OPERATING RANGES

Symbol

Parameter

Min

Typ

Max

Unit

VCC

Supply Voltage

54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

TA

Operating Ambient Temperature Range

54

74

– 55

0

25

25

125

70

°C

IOH

Output Current — High

54, 74

– 0.4

mA

IOL

Output Current — Low

54

74

4.0

8.0

mA