5-2

FAST AND LS TTL DATA

SN54/74LS166

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

PARALLEL

INPUTS

A

B

C

D

CLOCK INIHIBIT

CLOCK

SHIFT/LOAD

H

OUTPUT QH

G

F

E

CLEAR

SERIAL INPUT

H

H

H

H

H

L

L

L

H H

H

H

H

L

L

L

CLEAR

SERIAL SHIFT

LOAD

INHIBIT

SERIAL SHIFT

CLEAR

SERIAL INPUT

SHIFT/LOAD

A

B

C

D

H

G

F

E

(9)

(1)

(15)

(2)

(3)

(4)

(5)

(10)

(11)

(12)

(14)

(7)

(6)

CLOCK INHIBIT

CLOCK

(13)

R

CK

S

QA

R

CK

S

QB

R

CK

S

QC

R

CK

S

QD

R

CK

S

QE

R

CK

S

QF

R

CK

S

QG

R

CK

S

QH