5-457

FAST AND LS TTL DATA

SN54/74LS280

A

B

C

D

E

F

G

H

I

(8)

(9)

(10)

(11)

(12)

(13)

(1)

(2)

(4)

(5)

(6)

∑

EVEN

∑

ODD

FUNCTIONAL BLOCK DIAGRAM

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

VIH

Input HIGH Voltage

2.0

V

Guaranteed Input HIGH Voltage for

All Inputs

VIL

Input LOW Voltage

54

0.7

V

Guaranteed Input LOW Voltage for

All Inputs

VIL

Input LOW Voltage

74

0.8

V

Guaranteed Input LOW Voltage for

All Inputs

VIK

Input Clamp Diode Voltage

– 0.65

– 1.5

V

VCC = MIN, IIN = – 18 mA

VOH

Output HIGH Voltage

54

2.5

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOH

Output HIGH Voltage

74

2.7

3.5

V

VCC = MIN, IOH = MAX, VIN = VIH

or VIL per Truth Table

VOL

Output LOW Voltage

54, 74

0.25

0.4

V

IOL = 4.0 mA

VCC = VCC MIN,

VIN = VIL or VIH

per Truth Table

VOL

Output LOW Voltage

74

0.35

0.5

V

IOL = 8.0 mA

VIN = VIL or VIH

per Truth Table

IIH

Input HIGH Current

20

µA

VCC = MAX, VIN = 2.7 V

IIH

Input HIGH Current

0.1

mA

VCC = MAX, VIN = 7.0 V

IIL

Input LOW Current

– 0.4

mA

VCC = MAX, VIN = 0.4 V

IOS

Short Circuit Current (Note 1)

– 20

– 100

mA

VCC = MAX

ICC

Power Supply Current

27

mA

VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tPLH

tPHL

Propagation Delay, Data to Output

ΣEVEN

33

29

50

45

ns

CL = 15 pF

tPLH

tPHL

Propagation Delay, Data to Output

ΣODD

23

31

35

50

ns

CL = 15 pF