CS4294 datasheet(34/42 Pages) CIRRUS

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CS4294

DS326PP4

BIT_CLK - AC-link Serial Port Master Clock, Input/Output

This input/output signal controls the master clock timing for the AC-link. In codec primary

mode, this signal is an output 12.288 MHz clock signal which is divided down by two from the

XTL_IN input clock pin. In codec secondary mode, this signal is an input which controls the

AC-link serial interface. In BIT_CLK mode, this signal generates all internal clocking

including the AC-link serial interface timing. A series terminating resistor of 47

Ω should be

connected on this signal close to the CS4294 in primary mode or close to the BIT_CLK source

if in secondary mode.

SDATA_OUT - AC-link Serial Data Input Stream to AC ‘97, Input

This input signal transmits the control information and digital audio output streams to be sent

to the DACs. The data is clocked into the CS4294 on the falling edge of BIT_CLK. A series

terminating resistor of 47

Ω should be connected on this signal close to the device driving the

input.

SDATA_IN - AC-link Serial Data Output Stream from AC ‘97, Output

This output signal transmits the status information and digital audio input streams from the

ADCs. The data is clocked out of the CS4294 on the rising edge of BIT_CLK. A series

terminating resistor of 47

Ω should be connected on this signal as close to the CS4294 as

possible.

XTL_IN - Crystal Input

This pin accepts either a crystal, with the other pin attached to XTL_OUT, or an external

CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except

when operating in BIT_CLK mode. The crystal frequency must be 24.576 MHz and designed

for fundamental mode, parallel resonance operation.

XTL_OUT - Crystal Output

This pin is used for a crystal placed between this pin and XLT_IN. If an external clock is used

on XTL_IN or the codec is in BIT_CLK mode, this pin must be left floating with no traces or

components connected to it.

ID1#, ID0# - Codec ID, Inputs

These pins select the codec ID and mode of operation for the CS4294. They are sampled after

the rising edge of RESET# and not used after. These inputs have internal 100 k

Ω pull-ups and

should be left floating for a logic 0 or tied to analog ground for a logic 1. The pins utilize

inverted logic, so the condition of both pins floating sets the codec to primary mode while any

other combination sets the codec to a secondary mode. In primary mode, the codec is always

clocked from an external crystal or an external oscillator connected to the XTL_IN and/or

XTL_OUT pins with BIT_CLK as an output. In secondary mode, the clocking mechanism is

determined by the state of the BCM# pin with BIT_CLK always being an input.

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