CS4298 datasheet(20/52 Pages) CIRRUS

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CS4298

DS315PP2

5.5

AC ’97 Reset Modes

Three methods of resetting the CS4298, as defined in the AC ’97 Specification, are supported: Cold

AC ’97 Reset, Warm AC ’97 Reset, and AC ’97 Register Reset. A Cold AC ’97 Reset is required to

restart the AC-link when bit PR5 is set in the Power Down Control/Status (Index 26h) register.

5.5.1

Cold AC ‘97 Reset

A Cold Reset is performed by asserting RESET# in accordance with the minimum timing specifica-

tions in the Serial Port Timing section. Once de-asserted, all of the Codec’s registers will be reset to

their default power-on states and the BIT_CLK clock and SDATA_IN signals will be reactivated.

The timing of power-up/reset events is discussed in detail in the Power Management section.

5.5.2

Warm AC ’97 Reset

The CS4298 may also be reactivated when the AC-link is powered down (refer to the PR4 bit de-

scription in the Power Management section) by a Warm Reset. A Warm Reset allows the AC-link to

be reactivated without losing information in the Codec’s registers. Warm Reset is initiated when the

SYNC signal is driven high for at least 1 µs and then driven low in the absence of the BIT_CLK clock

signal. The BIT_CLK clock will not restart until at least 2 normal BIT_CLK clock periods

(± 162.8 ns) after the SYNC signal is de-asserted.

5.5.3

AC ’97 Register Reset

The third reset mode provides a register reset to the CS4298. This is available only when the

CS4298’s AC-link is active and the Codec Ready bit is set. The audio and modem subsections may

be reset independently. Any write to Reset (Index 00h) register will reset the audio subsection while

any write to Ext’d Modem Ctrl/Stat (Index 3Eh) register will reset the modem subsection. See the

respective register descriptions for additional information.

5.6

AC-Link Protocol Violation - Loss of SYNC

The CS4298 is designed to handle SYNC protocol violations. The following are situations where the

SYNC protocol has been violated:

• The SYNC signal is not sampled high for exactly 16 BIT_CLK clock cycles at the start of an

audio frame.

• The SYNC signal is not sampled high on the 256th BIT_CLK clock period after the previous

SYNC assertion.

• The SYNC signal goes active high before the 256th BIT_CLK clock period after the previous

SYNC assertion.

Upon loss of synchronization with the Controller, the Codec will mute all analog outputs and clear

the Codec Ready bit in the serial data input frame until two valid frames are detected. During this

detection period, the Codec will ignore all register reads and writes and will discontinue the trans-

mission of PCM capture data.

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