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CS43L41 Arkusz danych(PDF) 16 Page - Cirrus Logic

Numer części CS43L41
Szczegółowy opis  Low Power 24-Bit, 96 kHz DAC with Volume Control?
PDF  36 Pages
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L41 Arkusz danych(HTML) 16 Page - Cirrus Logic

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CS43L41
16
DS473PP1
4.3
DIGITAL INTERFACE FORMAT
Mode Control Register (address 01h)
Access:
R/W in I2C and write only in SPI.
Default:
0 - Format 0 (I2S, up to 24-bit data, 64 x Fs Internal SCLK)
Function:
The required relationship between the Left/Right clock, serial clock and serial data is defined by the
Digital Interface Format and the options are detailed in Figures 20-26.
4.4
DE-EMPHASIS CONTROL
Mode Control Register (address 01h)
Access:
R/W in I2C and write only in SPI.
Default:
0 - Disabled
Function:
Implementation of the standard 15
µs/50µs digital de-emphasis filter response, Figure 27, requires re-
configuration of the digital filter to maintain the proper filter response for 32, 44.1 or 48 kHz sample
rates. NOTE: De-emphasis is not available in High-Rate Mode.
765
4321
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
DIF2
DIF1
DIF0
DESCRIPTION
FORMAT
FIGURE
00
0
I2S, up to 24-bit data, 64 x Fs Internal SCLK
020
00
1
I2S, up to 24-bit data, 32 x Fs Internal SCLK
121
0
1
0
Left Justified, up to 24-bit data
2
22
0
1
1
Right Justified, 24-bit Data
3
23
1
0
0
Right Justified, 20-bit Data
4
24
1
0
1
Right Justified, 16-bit Data
5
25
1
1
0
Right Justified, 18-bit Data
6
26
1
1
1
Identical to Format 1
7
20
Table 3. Digital Interface Formats
765
4321
0
AMUTE
DIF2
DIF1
DIF0
DEM1
DEM0
POR
PDN
DEM1
DEMO
DESCRIPTION
0
0
Disabled
01
44.1kHz
10
48kHz
11
32kHz
Table 4. De-emphasis Filter Configurations



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