HM5259165B datasheet(10/63 Pages) ELPIDA

10 / 63 page

HM5259165B/HM5259805B/HM5259405B-75/A6

Data Sheet E0118H10

SS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the

output buffer.)

Command Operation

Command Truth Table

The SDRAM recognizes the following commands specified by the

CS, RAS, CAS, WE and address pins.

CKE

Command

Symbol

n - 1 n

CS RAS CAS WE BA0/BA1 A10

to A12

Ignore command

DESL

××

No operation

NOP

××

Column address and read command READ

Read with auto-precharge

READ A

Column address and write command WRIT

Write with auto-precharge

WRIT A

Row address strobe and bank active ACTV

Precharge select bank

PRE

Precharge all bank

PALL

Refresh

REF/SELF H

××

Mode register set

MRS

Note:

H: V

IH.

L: V

IL.

×: V

IH or VIL.

V: Valid address input

Ignore command [DESL]: When this command is set (

CS is High), the SDRAM ignore command input at

the clock. However, the internal status is held.

No operation [NOP]: This command is not an execution command. However, the internal operations

continue.

Column address strobe and read command [READ]: This command starts a read operation. In addition,

the start address of burst read is determined by the column address (AY0 to AY9; HM5259165B, AY0 to

AY9, AY11; HM5259805B, AY0 to AY9, AY11, AY12; HM5259405B) and the bank select address (BS).

After the read operation, the output buffer becomes High-Z.

Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a

burst read with a burst length of 1, 2, 4 or 8.

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