12 www.microsemi.com/products/fpga-soc/fpga/proasic3l

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. AES is not available for Cortex-M1 ProASIC3L devices.

3. For the A3PE3000L, the PQ208 package has six CCCs and two PLLs.

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the packaging section of the datasheet to ensure you are complying with design and board migration requirements.

2. For A3P250L devices, the maximum number of LVPECL pairs in east and west banks cannot exceed 15.

3. ARM Cortex-M1 support is TBD on this device.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. FG256 and FG484 are footprint-compatible packages.

6. “G” indicates RoHS-compliant packages. Refer to “ProASIC3L Ordering Information” on page 3 of the datasheet for the location of the “G” in the part number.

7. For A3PE3000L devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

8. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not as a regular I/O, the number of single-ended user I/Os available is reduced by one.

ProASIC3L

Balancing low power, performance and low cost

ProASIC3L FPGAs feature 40 percent lower dynamic power and 90 percent lower static power than the previous generation ProASIC3 FPGAs and orders of

magnitude lower power than SRAM competitors, combining dramatically reduced power consumption with up to 350 MHz operation. The ProASIC3L family also

supports the free implementation of an FPGA-optimized 32-bit ARM Cortex-M1 processor, enabling system designers to select Microsemi’s flash FPGA solution

that best meets their speed and power design requirements, regardless of application or volume. Optimized software tools using power-driven layout (PDL)

provide instant power reduction capabilities.

ProASIC3L Low Power Devices

ProASIC3L Devices

A3P250L

A3P600L

A3P1000L

A3PE3000L

M1A3P600L

M1A3P1000L

M1A3PE3000L

System Gates

250,000

600,000

1,000,000

3,000,000

VersaTiles (D-flip-flops)

6,144

13,824

24,576

75,264

RAM (1,024 bits)

36

108

144

504

4,608-Bit Blocks

8

24

32

112

FlashROM Kbits (1,024 bits)

1

1

1

1

Yes

Yes

Yes

Yes

1

1

1

6

VersaNet Globals

18

18

18

18

I/O Banks

4

4

4

8

Maximum User I/Os

(packaged device)

157

235

300

620

Package Pins

VQ

PQ

FG

VQ100

PQ208

FG144, FG256

PQ208

FG144, FG256, FG484

PQ208

FG144, FG256, FG484

PQ208

FG324, FG484, FG896

ProASIC3L Devices

A3P600L

A3P1000L

A3PE3000L

ARM Cortex-M1 Devices

M1A3P600L

M1A3P1000L

I/O Type

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

Single-

Differential

I/O Pairs

VQ100

68

13

—

—

—

—

—

—

PQ208

151

34

154

35

154

35

147

65

FG144

97

24

97

25

97

25

—

—

FG256

157

38

177

43

177

44

—

—

FG324

—

—

—

—

—

—

221

110

FG484

—

—

235

60

300

74

341

168

FG896

—

—

—

—

—

—

620

310

• Low power 1.2 V to 1.5 V

core operation

• 700 Mbps DDR, LVDS

capable I/Os

• Up to 350 MHz

system performance

• Configuration memory error

immune

• ISP and security

• Flash*Freeze technology

for low power