®

RF Monolithics, Inc.

Phone: (972) 233-2903

Fax: (972) 387-9148

E-mail: info@rfm.com

Page 1 of 2

RFM Europe

Phone: 44 1963 251383

Fax: 44 1963 251510

http://www.rfm.com

©1999 by RF Monolithics, Inc. The stylized RFM logo are registered trademarks of RF Monolithics, Inc.

SC3048B-022806

Electrical Characteristics

Characteristic

Sym

Notes

Minimum

Typical

Maximum

Units

Output Frequency

Absolute Frequency

1, 2

443.911

444.089

MHz

Tolerance from 444.000 MHz

∆f

O

±200

ppm

Q and Q Output

Voltage into 50

Ω (VSWR ≤ 1.2)

1, 3

0.5

4.5

dBm

Operating Load VSWR

2:1

Symmetry

3, 4, 5

49

51

%

Harmonic Spurious

3, 4, 6

-30

dBc

Nonharmonic Spurious

-60

dBc

Q and Q Period Jitter

3, 4, 6, 7

15

30

3, 4, 7, 8

35

Output (Disabled)

Amplitude into 50

Ω

3, 9

75

Output DC Resistance (between Q & Q)

3

100

K

Ω

ENABLE (Terminal 14)

Input HIGH Voltage

3, 9

V

Input LOW Voltage

0.0

0.20

V

Input HIGH Current

3

5

mA

Input LOW Current

-1

mA

Propagation Delay

1

ms

DC Power Supply

Operating Voltage

1, 3

+3.13

+3.30

+3.47

VDC

Operating Current

18

40

mA

Operating Ambient Temperature

1, 3

0

+70

°C

Lid Symbolization (YY = Year, WW = Week)

RFM SC3048B 444.00 MHz YYWW

•

Quartz SAW Frequency Stability

•

Fundamental Fixed Frequency

•

Excellent Jitter and Symmetry

•

Rugged, Miniature, Surface-Mount Case

•

Low-Voltage Power Supply (3.3 VDC)

•

Directive 2002/95/EC (ROHS) Compliant by June, 2006

This digital clock is designed for use in critical timing applications. Fundamental-mode oscillation is made pos-

sible by surface-acoustic-wave (SAW) technology. The design results in low jitter, compact size, and low pow-

er consumption. Differential outputs provide a sine wave that is made to drive 50

Ω loads.

Absolute Maximum Rating

Value

Units

0 to +4.0

VDC

Input Voltage (ENABLE at Terminal 8)

0 to +4.0

VDC

Case Temperature (Powered or Storage)

-40 to +85

°C

444.0 MHz

Differential

Sine-Wave

Clock

SC3048B

SMC-8 Case

1.

Unless otherwise noted, all specifications include any combination of load

VSWR, VCC, and TA. In addition, Q and Q are terminated into 50

Ω loads to

ground. (See: Typical Test Circuit.)

2.

One or more of the following United States patents apply: 4,616,197; 4,670,681;

4,760,352.

3.

The design, manufacturing process, and specifications of this device are subject

to change without notice.

4.

Only under the nominal conditions of 50

Ω load impedance with VSWR ≤ 1.2 and

nominal power supply voltage.

5.

Symmetry is defined as the pulse width (in percent of total period) measured at

the 50% points of Q or Q. (See: Timing Definitions.)

6.

Jitter and other spurious outputs induced by externally generated electrical noise

regulation and careful PCB layout are recommended for optimum performance.

7.

Applies to period jitter of Q and Q. Measurements are made with the Tektronix

CSA803 signal analyzer with at least 1000 samples.

8.

9.

The outputs are enabled when Terminal 8 is at logic HIGH. Propagation delay is

defined as the time from the 50% point on the rising edge of ENABLE to the 90%

point on the rising edge of the output amplitude or as the fall time from the 50%

point to the 10% point. (SEE: Timing Definitions.)

CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.

NOTES: