MB40C318VPFV datasheet(11/16 Pages) FUJITSU

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MB40C318V

s TIMING DIAGRAM 3

Differential CLK input-demultiplex output (two-phase) mode

• CLKEP = CLKEN = 140 MHz (max)

• CLKA = CLKB = “L” (DVSS)

• CKSEL = “L” (AVSS)

•DSEL = “H” (DVDD)

•CE = “L” (AVSS)

•OE = “L” (DVSS)

• Differential CLK input — Solid line: CLKEP, Dotted line: CLKEN

•VINA input — Sampling at CLKEP rising

(CLKEN falling)

•DA0 to DA7 — Output (after 5 CLK + tpdM2 from Sampling) at CLKEP rising

(CLKEN falling)

•DB0 to DB7 — Output (after 5 CLK + tpdM2 from Sampling) at CLKEP rising

(CLKEN falling)

VIHD

VILD

VOHD

VOLD

VOHD

VOLD

VINA input

DB0 to DB7

DA0 to DA7

VOHD

VOLD

CLKOA

VOHD

VOLD

CLKOB

VOHD

VOLD

tAD

DVDDI

− 1.1 V

+ 1N + 2N + 3N + 4N + 5

+ 10

+ 9

+ 8

+ 7

+ 6

tWS+

tWS−

DVDDI

− 1.45 V

or N

− 10

or N

− 9

or N

− 8

or N

− 8

− 5

or N

− 6

− 3

or N

− 4

− 1

or N

− 2

0.4 V

DVDD

− 0.4 V

tpdM2(max)

tpdM2(typ)

0.4 V

DVDD

− 0.4 V

tpdM2(max)

tpdM2(typ)

tpdM2(min)

0.4 V

DVDD

− 0.4 V

tpdM2O(max)

tpdM2O(typ)

tpdM2O(min)

0.4 V

DVDD

− 0.4 V

tpdM2O(max)

tpdM2O(typ)

tpdM2O(min)

or N

− 9

− 8

or N

− 7

− 8

or N

− 7

− 6

or N

− 5

− 4

or N

− 3

− 2

1.5 V

tpdM2(min)

+ 1

− 3N − 2N − 1

+ 3

+ 2

− 10

− 9

− 7

Differential

CLK input

RESET input

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