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ST1S32 Arkusz danych(PDF) 12 Page - STMicroelectronics |
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ST1S32 Arkusz danych(HTML) 12 Page - STMicroelectronics |
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12 / 29 page ![]() Functional description ST1S32 12/29 Doc ID 023246 Rev 1 Equation 12 So, closing the loop, the loop gain GLOOP(s) is: Equation 13 Example: VIN=5 V, VOUT=1.2 V, Iomax=4 A, L=1.0 uH, Cout=47 uF (MLCC), R1=10 k Ω, R2=20 k Ω (see Section 5.2 and Section 5.3 for inductor and output capacitor selection guidelines). The module and phase Bode plot are reported in Figure 6. The bandwidth is 117 kHz and the phase margin is 63 degrees. Figure 6. Module Bode plot f Z 36 2 kHz , = f P LF 30 Hz = G LOOP s () G CO s () G DIV s () G EA s () ⋅⋅ = 0.1 1 10 100 1 .10 3 1 .10 4 1 .10 5 1 .10 6 1 .10 7 60 42 24 6 12 30 48 66 84 102 120 Frequency [Hz] AM11420v1 |
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