COM

Y

Y2

A

INH

Y1

COM

5

2

7

6

1

SW

SW

NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals can

be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.

SN74LVC2G53

SCES324N – JULY 2001 – REVISED JANUAY 2014

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Function Table

CONTROL

ON

INPUTS

CHANNEL

INH

A

L

L

Y1

L

H

Y2

H

X

None

Logic Diagram (Positive Logic)

Simplified Schematic, Each Switch (SW)

2

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