PS20230 datasheet(7/26 Pages) ETC2

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PS20230

PLESSEY SEMICONDUCTORS LTD

TAMERTON ROAD | ROBOROUGH | PLYMOUTH | DEVON | PL6 7BQ

2 Pin definitions

Name

Pin description

I/O

Note

Not connected

1, 2, 67, 68, 70,

71,74,75

76,77,80

2-wire bus

CLK1

EEPROM Master 2-wire bus clock

I/O

Open drain

Fall time control

DATA1

EEPROM Master 2-wire bus data

I/O

Open drain

Fall time control

CLK2

Tuner Master 2-wire bus clock

I/O

Open drain

Fall time control

DATA2

Tuner Master 2-wire bus data

I/O

Open drain

Fall time control

ADFMT

EEPROM address format

CMOS

3.3

Crystal

XTIB

Low phase noise oscillator cell. A 24

CMOS

XTO

MHz crystal must be used

CMOS

GPP’s

3,8,16,17,18

GPP(7:0)

General Purpose Ports

I/O

CMOS Tristate / push-

3.3

19,20,23,

pull

AGC

AGC1

IF AGC o/p

Open drain

AGC2

RF AGC o/p, should be tied to ground

Open drain

when not used

RFLEV

RF AGC level indicator input

Analog

Control

SLEEP

Suspend mode power down for rest of

CMOS

3.3

PCB. High = suspend, low = powered

RESETB

Active low reset pin

CMOS

Infra-red

IRDI

Infra-red input

CMOS

3.3

USB

USBP

USB positive data

I/O

Differential Analog

USBM

USB negative data

I/O

Differential Analog

RES1K5

USB pull up resistor

I/O

3.3

RES6K2

USB bias resistor

I/O

Digital power

pins

PLLVDD

PLL and clocking supply

1.8

PLLGND

PLL ground supply

9,11, 13,

CVDD

Demodulator core logic power supply

1.8

26,56.79

15,57,64

CUVDD

USB core logic power supply

1.8

6,21,73

IVDD

I/O ring power supply

3.3

7, 10, 12, 14,

VSS

Logic Core and I/O ground

22, 33, 58,

61,72,78

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