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ML7344J Arkusz danych(PDF) 131 Page - List of Unclassifed Manufacturers |
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ML7344J Arkusz danych(HTML) 131 Page - List of Unclassifed Manufacturers |
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131 / 151 page ![]() FEDL7344C/E/J-04 ML7344C/E/J 131/151 ○RX During RX, if PLL unlock is detected, PLL unlock interrupt (INT[2] group1) will be generated. During RX, even if PLL unlock is detected, RX state is maintained (do not move to IDLE state). Please receive next packet after clearing PLL unlock interrupt. When PLL unlock interrupt occurs frequently, PLL unlock cause mitgh be due to the mismatch of the VCO circuit and using frequency band. Please use after removing the cause by circuit verification. START No Next packet to be received? Yes PLL unlock (INT[2])? [INT_SOURCE_GRP1:B0 0x0D (2)] Normal RX (To RX flowchart) No Yes END INT[2] clear [INT_SOURCE_GRP1:B0 0x0D(2)] RX_ON issue [RF_STATUS:B0 0x0B] Force_TRX_OFF issue [RF_STATUS:B0 0x0B] |
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