HD74ACT166 datasheet(2/11 Pages) HITACHI

2 / 11 page

HD74AC166/HD74ACT166

Logic Symbol

PE P0

VCC=Pin16

GND=Pin8

P1 P2 P3

P4 P5 P6 P7

913

10 11 12 14

Pin Names

1, CP2

Clock Pulse Inputs (Active Rising Edge)

Serial Data Input

Parallel Enable Input (Active Low)

0 to P7

Parallel Data Inputs

Asynchronous Master Reset Input (Active Low)

Last Stage Output

Functional Description

Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of

either clock input if the other clock input is Low. When one of the clock inputs is used as an active High

clock inhibt, it should attain the High state while the other clock is still in the High state following the

previous operation. When the Parallel Enable (

PE) input is Low, data is loaded into the register from the

Parallel Data (P

0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted

from the Serial Data (D

S) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 → Q1, Q1

→ Q

2, etc.) on the rising edge of the clock.

HD74ACT166 Arkusz danych(PDF) 2 Page - Hitachi Semiconductor