Timing Diagrams

Read cycle 1 output enable controlled (1)

Read cycle 2 address controlled (1, 2, 4)

Read cycle 3 chip select controlled (1, 3, 4)

Note:

1. WE is high for read cycle

3. Address is valid prior to or coincident with the CS transition low

5. Transition is measured at

±500mV from the steady state

HT62L256

Rev. 0.00

5

August 15, 2002

Preliminary

A d d r e s s

D o n ' t C a r e

U n u s e d

A d d r e s s

D o n ' t C a r e

U n u s e d

A d d r e s s

O E

C S

D o n ' t C a r e

U n u s e d