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GMS90C320PL40 Arkusz danych(PDF) 42 Page - Hynix Semiconductor |
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GMS90C320PL40 Arkusz danych(HTML) 42 Page - Hynix Semiconductor |
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42 / 46 page ![]() GMS90C320 38 OCT. 2000 Ver 1.2 Figure 7 AC Testing: Input, Output Waveforms Figure 8 Float Waveforms Figure 9 External Clock Cycle AC Inputs during testing are driven at VCC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’. 0.2VCC + 0.9 0.2VCC − 0.1 Test Points VCC−0.5V 0.45V Timing measurements are made a VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. VLOAD + 0.1 VLOAD − 0.1 Timing Reference Points 0.2VCC − 0.1 VOH − 0.1 VOL + 0.1 VLOAD For timing purposes a port pin is no longer floating when a 100mV change from load voltage IOL /IOH ≥ 20mA. occurs and begins to float when a 100mV change from the loaded VOH /VOL level occurs. tCHCL tCLCH tCLCX tCLCL tCHCX 0.2 VCC −0.1 0.7 VCC VCC−0.5V 0.45V |
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