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HDM8513 Arkusz danych(PDF) 16 Page - Hynix Semiconductor |
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HDM8513 Arkusz danych(HTML) 16 Page - Hynix Semiconductor |
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16 / 67 page ![]() 16 Table 11: Output Timing Symbol Parameter Min. Max. Unit tsu Output Data Setup before DATA_CLK and DATA_STB 5 - ns thd Output Data Hold after DATA_CLK and DATA_STB 10 - ns DATA_CLK DATA_STB FRAME_SYNC DATA_VALID DATA 1 2 3 4 n n-1 n-2 n-3 xx xx xx xx xx xx xx xx xx tsu t hd FIGURE 9: OUTPUT TIMING DIAGRAM FOR NORMAL PARALLEL DATA_CLK DATA_STB FRAME_SYNC DATA_VALID DATA[0] 1 2 3 4 8n-5 8n-6 8n-7 8n-8 xx xx tsu t hd xx xx 8n-4 8n-3 8n-2 8n-1 8n FIGURE 10: OUTPUT TIMING DIAGRAM FOR NORMAL SERIAL NOTE : In case of DVB, n is 188 In case of DSS, n is 144 |
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