PCF8534A datasheet(21/52 Pages) NXP

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PCF8534A

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Product data sheet

Rev. 6 — 25 July 2011

21 of 52

NXP Semiconductors

PCF8534A

Universal LCD driver for low multiplex rates

In cascaded applications each PCF8534A in the cascade must be addressed separately.

Initially, the first PCF8534A is selected by sending the device-select command matching

the first hardware subaddress. Then the data pointer is set to the preferred display RAM

address by sending the load-data-pointer command.

Once the display RAM of the first PCF8534A has been written, the second PCF8534A is

selected by sending the device-select command again. This time however the command

matches the hardware subaddress of the second device. Next the load-data-pointer

command is sent to select the preferred display RAM address of the second PCF8534A.

This last step is very important because during writing data to the first PCF8534A, the

data pointer of the second PCF8534A is incremented. In addition, the hardware

subaddress should not be changed while the device is being accessed on the I2C-bus

interface.

7.10.3 RAM writing in 1:3 multiplex drive mode

In 1:3 multiplex drive mode, the RAM is written as shown in Table 7 (see Figure 13 as

well).

If the bit at position BP2/S2 would be written by a second byte transmitted, then the

mapping of the segment bits would change as illustrated in Table 8.

In the case described in Table 8 the RAM has to be written entirely and BP2/S2, BP2/S5,

BP2/S8, and so on, have to be connected to elements on the display. This can be

achieved by a combination of writing and rewriting the RAM like follows:

Table 7.

Standard RAM filling in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

---

Table 8.

Entire RAM filling by rewriting in 1:3 multiplex drive mode

Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.

Display RAM

bits (rows)/

backplane

outputs (BPn)

Display RAM addresses (columns)/segment outputs (Sn)

a1/b7 b4

b1/c7 c4

c1/d7 d4

d1/e7 e4

a0/b6 b3

b0/c6 c3

c0/d6 d3

d0/e6 e3

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