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ICS542M Arkusz danych(PDF) 3 Page - Integrated Circuit Systems

Numer części ICS542M
Szczegółowy opis  Clock Divider
PDF  4 Pages
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Producent  ICST [Integrated Circuit Systems]
Strona internetowa  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS542M Arkusz danych(HTML) 3 Page - Integrated Circuit Systems

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ICS542
Clock Divider
MDS 542 B
3
Revision 050400
Printed 11/14/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
C
Soldering Temperature
Max of 10 seconds
260
C
Storage temperature
-65
150
C
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
(VDD/2)-1
V
Input High Voltage, VIH
S0, S1, OE
2
V
Input Low Voltage, VIL
S0, S1, OE
0.8
V
Output High Voltage, VOH, CMOS levels
IOH=-4mA
VDD-0.4
V
Output High Voltage, VOH
IOH=-12mA
2.4
V
Output Low Voltage, VOL
IOL=4mA
0.4
V
IDD Operating Supply Current, 100 MHz input No Load, 5.0V, 11 sel
11
mA
IDD Operating Supply Current, 100 MHz input No Load, 3.3V, 11 sel
7
mA
Short Circuit Current
Each Output
±40
mA
Input Capacitance, S1, S0, OE
Pins 4, 5, 6
4
pF
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, clock input
at VDD = 5V
0
156
MHz
Input Frequency, clock input
at VDD = 3.3V
0
156
MHz
Skew of output clocks
rising edges at VDD/2
500
ps
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
at VDD/2
45
49 to 51
55
%



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