IDT7132LA55JI datasheet(13/16 Pages) IDT

13 / 16 page

6.42

IDT7132SA/LA and IDT 7142SA/LA

High Speed 2K x 8 Dual Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)

Timing Waveform of BUSY Arbitration Controlled

by Address Match Timing(1)

Truth Tables

Table I. Non-Contention Read/Write Control(4)

NOTES:

1. A0L - A10L

≠ A0R - A10R

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.

4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE

tAPS

(2)

ADDR

"A"

and "B"

ADDRESSES MATCH

tBAC

tBDC

CE"B"

CE"A"

BUSY"A"

2692 drw 13

BUSY"B"

ADDRESSES DO NOT MATCH

ADDRESSES MATCH

tAPS

(2)

ADDR"A"

ADDR"B"

2692 drw 14

tBAA

tBDA

tRC or tWC

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).

Left or Right Port(1)

R/W

D0-7

Function

Port Disabled and in Power-Down Mode, ISB2 or ISB4

CER

= CEL = VIH, Power-Down Mode, ISB1 or ISB3

DATAIN

Data on Port Written into Memory(2)

DATAOUT

Data in Memory Output on Port(3)

High Impedance Outputs

2692 tbl 12

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