6-8

Read Cycle Dynamic Electrical Specifications

PARAMETER

SYMBOL

(V)

UNITS

MIN

MAX

MIN

MAX

Data Access Time (Note 1)

5

-

190

-

255

ns

Read Cycle Time

5

190

-

255

-

ns

Output Enable Time

5

65

-

90

-

ns

Output Disable Time

5

-

65

-

90

ns

NOTE:

1. 100% testing. All other limits are designer’s parameters under given test conditions and do not represent 100% testing.

NOTES:

1. Chip-Select (CS) permitted to change from high to low level or remain low on a selected device.

2. Chip-Select (CS) permitted to change from low to high level or remain low.

3. Read/Write (R/W) must be at a high level during all address transitions.

4. Don’t care.

FIGURE 1. READ CYCLE TIMING DIAGRAM

CS

A0 - A9

R/W

DATA OUT

(NOTE 3)

(NOTE 5)

(NOTE 1)

(NOTE 2)

(NOTE 4)

(NOTE 5)

HIGH

IMPEDANCE

DATA OUT

VALID

CDP1821C/3