ADAV802_15 datasheet(13/53 Pages) AD

13 / 53 page

Preliminary Technical Data

ADAV802

Rev. Pr G | Page 13 of 53

Selecting A Sample Rate

The sample rate of the ADC is always 256 × fS. To facilitate

different MCLKs the ADC block has a programmable divider

which allows the MCLK to be divided by 1, 2 or 3 before being

applied to the ADC. This allows for MCLKs of 256 × fS , 512 × fS

or 768 × fS to be applied to the ADC. To synchronize the data

output port with the ADC the same divider setting should be

applied to the Internal Clock (ICLK1 or ICLK2) which is

controlling the output port. The Internal Clock dividers are

shown in Figure 34. By default the ∑∆ modulator runs at ADC

MCLK/2. The modulator is designed to run with a maximum

clock rate of 6.144MHz,. For cases where higher sample rates

would run the modulator at speeds higher than this the user can

select divide the ADC MCLK by 4 before it is applied to the

modulator. To compensate for this the modulator uses an

alternate filter configuration. The divide setting is selected by

the AMC bit in ADC Control Register 1.

Automatic Level Control (ALC)

The ADC record channel features a programmable automatic

level control block. This block monitors the level of the ADC

output signal and will automatically reduce the gain if the signal

at the input pins causes the ADC output to exceed a preset limit.

This function can be useful to maximize the signal dynamic

range when the input level is not well-defined. The PGA can be

used to amplify the unknown signal and the ALC will reduce

the gain until the ADC output is within the preset limits. This

results in maximum front-end gain. Since the ALC block

monitors the output of the ADC the volume control function

should not be used. The ADC volume control scales the results

from the ADC and any distortion caused by the input signal

exceeding the input range of the ADC will still be present at the

output of the ADC but scaled by a value determined by the

volume control register. The ALC block consists of two

functions, Attack Mode and Recovery Mode. The Recovery

Mode consists of three settings, namely, No Recovery, Normal

Recovery and Limited Recovery. Each of these modes in

discussed in detail below. Figure 6 shows an overall flow

diagram of the ALC block.

Attack Mode

When the absolute value of the ADC output exceeds the level

set by the Attack Threshold bits in the ALC Control Register 2,

Attack Mode is initiated. The PGA gain for both channels is

reduced by one step (0.5dB). The ALC will then wait for a time

determined by the Attack Timer bits before sampling the ADC

output value again. If the ADC output is still above the

threshold the PGA gain is reduced by a further step. This

procedure continues until the ADC output is below the limit set

by the Attack Threshold bits. The initial gains of the PGAs are

defined by ADC Left PGA Gain Register and ADC Right PGA

Gain Register and may be different values. The ALC simply

adds or subtracts a common gain offset to these values. The

ALC will preserve any gain difference in dB as defined by those

registers. At no time will the PGA gains exceed their initial

values. Therefore, the initial gain setting also serves as a

maximum value.

The Limit Detection Mode bit in ALC Control Register 1

determines how the ALC should respond to an ADC output

which exceeds the set limits. If this bit is a one then both

channels must exceed the threshold before the gain is reduced.

This mode can be used to prevent unnecessary gain reduction

due to spurious noise on a single channel. If the Limit Detection

Mode bit is a zero the gain will be reduced when either channel

exceeds the threshold.

No Recovery Mode

By default there is no gain recovery. Once the gain has been

reduced it will not be recovered until the ALC has been reset, by

toggling the ALCEN bit in ALC Control Register 1 or by writing

any value to ALC Control Register 3. The latter option is more

efficient as it requires only one write operation to reset the ALC

function. No Recovery Mode prevents volume modulation of

the signal, caused by adjusting the gain, which can create

undesirable artifacts in the signal. Since the gain can be reduced

but not recovered, care should be taken that spurious signals do

not interfere with the input signal as these may trigger a gain

reduction unnecessarily.

Normal Recovery

This mode allows for the PGA gain to be recovered providing

that the input signal meets certain criteria. Firstly, the ALC must

not be in Attack Mode, i.e., the PGA gain has been reduced

sufficiently such that the input signal is below the level set by

the Attack Threshold bits. Secondly, the output result from the

ADC must be below the level set by the Recovery Threshold bits

in ALC Control Register. If both of these criteria are met the

gain is recovered by one step (0.5dB). The gain is incrementally

restored to its original value assuming the ADC output level is

below the Recovery Threshold at intervals determined by the

Recovery Time bits. Should the ADC output level exceed the

Recovery Threshold while the PGA gain is being restored the

PGA gain value will be held and will not continue restoration

until the ADC output level is again below the Recovery

Threshold. Once the PGA gain is restored to its original value it

will not be changed again unless the ADC output value exceeds

the Attack Threshold and the ALC then enters Attack Mode.

Care should be exercised when using this mode to choose

values for the Attack and Recovery thresholds to prevent

excessive volume modulation caused by continuous gain

adjustments.

Limited Recovery

Limited Recovery Mode offers a compromise between No

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