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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADE7166 Arkusz danych(PDF) 12 Page - Analog Devices |
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ADE7166 Arkusz danych(HTML) 12 Page - Analog Devices |
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12 / 152 page  ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569 Rev. B | Page 12 of 1 52 Table 8. SPI Master Mode Timing (SPICPHA = 0) Parameters Parameter Description Min Typ Max Unit tSL SCLK low pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns tSH SCLK high pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns tDAV Data output valid after SCLK edge 3 × tCORE1 ns tDOSU Data output setup before SCLK edge 75 ns tDSU Data input setup time before SCLK edge 0 ns tDHD Data input hold time after SCLK edge tCORE1 ns tDF Data output fall time 19 ns tDR Data output rise time 19 ns tSR SCLK rise time 19 ns tSF SCLK fall time 19 ns 1 tCORE depends on the clock divider or CD[2:0] bits of the POWCON SFR, Address 0xC5 (see Table 26); tCORE = 2CD/4.096 MHz. SCLK (SPICPOL = 0) t DSU SCLK (SPICPOL = 1) MOSI MISO MSB LSB LSB IN BITS [6:1] BITS [6:1] t DHD t DR t DAV t DF t DOSU t SH t SL t SR t SF MSB IN Figure 6. SPI Master Mode Timing (SPICPHA = 0) |
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