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AN4035 Arkusz danych(PDF) 22 Page - STMicroelectronics |
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AN4035 Arkusz danych(HTML) 22 Page - STMicroelectronics |
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22 / 42 page  On-Chip Emulation (OnCE) AN4035 22/41 Doc ID 022669 Rev 2 Figure 17. CPU status and control scan chain register 3.7.1 Instruction Register (IR) After entering debug mode, the opcode of the next instruction to be executed is in the instruction register (IR). The value in the IR should be saved for later restoration if continuation of the normal instruction stream is desired. The external tool has the capability to put instructions directly into the instruction register (IR) via the CPUSCR. These instructions can then be executed by the debug control block. By selecting appropriate instructions and single stepping them, the external tool can examine or change memory locations or CPU registers. WBBRlow WBBRhigh MSR PC IR CTL TDO TCK TDI |
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