AN1313 - APPLICATION NOTE

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5 - NEW REGISTERS

5.1 - New Registers Impacting the Application

This section presents new registers that have to be considered when porting an application running on

the ST10F168 onto the ST10F269.

5.1.1 - XPERCON Register

The ST10F269 has a new register named XPERCON that allows the XBUS peripherals to be separately

selected for being visible to the user by means of corresponding bits. If not selected (not activated with a

bit of XPERCON) before the XPEN bit in SYSCON is set, the corresponding address space, port pins

and interrupts are not occupied by the peripheral, and thus this peripheral is not visible and not available.

ST10F269: XPERCON (F024h / 12h)

ESFR

Reset Value: 0005h

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

---

---

---

--

RTCEN XRAM2EN XRAM1EN

CAN2EN

CAN1EN

RW

RW

RW

RW

RW

Table 3 : XPERCON Register Bits

Bit

Number

Bit Name

Function

Reset

Value

0

CAN1EN

0

1

CAN1 Enable Bit

Accesses to the on-chip CAN1 XPeripheral and its functions are dis-

abled (P4.5 and P4.6 pins can be used as general purpose IOs, but

address range 00’EE00h -00EFFFh is only directed to external memory

if CAN2EN is ’0’ also.)

The on-chip CAN1 XPeripheral is enabled and can be accessed.

1

1

CAN2EN

0

1

CAN2 Enable Bit

Accesses to the on-chip CAN2 XPeripheral and its functions are dis-

abled (P4.5 and P4.6 pins can be used as general purpose IOs, but

address range 00’EE00h -00EFFFh is only directed to external memory

if CAN1EN is ’0’ also.)

The on-chip CAN2 XPeripheral is enabled and can be accessed.

0

2

XRAM1EN

0

1

XRAM1 Enable Bit

Accesses to the on-chip 2KByte XRAM are disabled, external access

performed.

The on-chip 2KByte XRAM is enabled and can be accessed.

1

3

XRAM2EN

0

1

XRAM2 Enable Bit

Accesses to the on-chip 8KByte XRAM are disabled, external access

performed.

The on-chip 8KByte XRAM is enabled and can be accessed.

0

4

RTCEN

0

1

RTC Enable Bit

Accesses to the on-chip Real Time Clock are disabled, external access

performed. Address range 00’EC00h-00’EFFFh is only directed to exter-

nal memory if CAN1EN and CAN2EN are ‘0’ also.

The on-chip Real Time Clock is enabled and can be accessed.

0

5...15

Reserved