Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

AN4231 Arkusz danych(PDF) 9 Page - STMicroelectronics

Numer części AN4231
Szczegółowy opis  Standby mode exit from FLASH to RAM configuration settings
PDF  22 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  STMICROELECTRONICS [STMicroelectronics]
Strona internetowa  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4231 Arkusz danych(HTML) 9 Page - STMicroelectronics

Back Button AN4231 Datasheet HTML 5Page - STMicroelectronics AN4231 Datasheet HTML 6Page - STMicroelectronics AN4231 Datasheet HTML 7Page - STMicroelectronics AN4231 Datasheet HTML 8Page - STMicroelectronics AN4231 Datasheet HTML 9Page - STMicroelectronics AN4231 Datasheet HTML 10Page - STMicroelectronics AN4231 Datasheet HTML 11Page - STMicroelectronics AN4231 Datasheet HTML 12Page - STMicroelectronics AN4231 Datasheet HTML 13Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 22 page
background image
DocID024130 Rev 2
9/22
AN4231
STANDBY Mode transition
2
STANDBY Mode transition
Once STANDBY is entered, it is only left via a system wakeup. On exiting the STANDBY
mode, all power domains are powered up according to the settings in the PCU_PCONFn
registers, and the DRUN mode is entered. In DRUN mode, at least power domains 0 and 1
are powered.
Figure 3, shows an example for a mode transition from RUN0 to STANDBY to DRUN. All
power domains which have PCU_PCONFn.STBY cleared enter power-down phase. In this
example, only power domain 1 is disabled during STANDBY mode.
When the MC_PCU receives the mode change request to STANDBY mode, it starts the
power down phase for power domain 1. During the power down phase, clocks are disabled
and reset is asserted resulting in a loss of all the information for this power domain. Then
the power domain is disconnected from the power supply (power-down state).
Figure 3. MC_PCU Events During Power Sequences (STANDBY mode)
When the MC_PCU receives a system wakeup request, it starts the power-up phase. The
power domain is re-connected to the power supply and the voltage in power domain 1
increases slowly. Once the voltage is in an operable range, clocks are enabled and the reset
is deasserted (power-up state).
GAPGRI00364



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22


Arkusz danych Pobierz

Go To PDF Page


Link URL



Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Link do karty katalogowej    |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com