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AN3213

ST7570 demonstration board description

Doc ID 17429 Rev 1

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7.3

PCB layout guidelines

7.3.1

Thermal performance

The ST7570 device can operate within the standard industrial temperature range, from -40

to 85 °C ambient temperature. Especially in high ambient temperature conditions, the effect

of the power dissipation of the device must be considered to keep it operating in safe

conditions.

Even though the ST7570 features a built-in thermal shutdown circuitry which turns off the

power amplifier (PA) when the die temperature (TJ) exceeds 170 °C, it is recommended not

to exceed 125 °C during normal operation to ensure the functionality of the IC.

A QFN48 package with Exposed Pad has been chosen for the ST7570 device to achieve

very good thermal performance. However, in order to take full advantage of this, the PCB

must be designed to effectively conduct heat away from the package.

To obtain a low impedance thermal path to the PCB, a 5x5 mm thermal pad has been

realized on the top layer under the device. In order to effectively remove the heat, the

exposed pad must be well soldered to the PCB thermal pad. Therefore, the out-gassing

phenomenon due to the soldering process must be controlled to reduce solder voids

between the QFN48 exposed pad and the PCB thermal pad. To achieve this, smaller

multiple openings in the solder paste stencil should be used instead of one big opening on

the thermal pad region. This has also the advantage of reducing the amount of solder paste

used, therefore avoiding bridges with perimeter pads.

A suitable example for the QFN48 package is shown in Figure 35.

Figure 35.

Example of stencil openings for the QFN48 package

Another technique to improve heat conduction on the top layer is to fill all unused areas with

copper tied to the dissipating ground plane.

In order to have an effective heat transfer from the top layer of the PCB to the bottom layer,

thermal vias need to be included within the thermal pad area. If properly designed, thermal

vias are the most efficient paths for removing heat from the device.

An array of 4 x 4 thermal vias at 1.0 mm pitch, with a via diameter of 0.3 mm, have been

incorporated into the thermal pad, as shown in Figure 36 and 37.

To minimize solder wicking effect due to open vias, possibly leading to poor soldering of the

QFN48 exposed pad, the via encroaching technique has been adopted (see bottom-side

image in Figure 37). The bottom-side solder resist has only small openings (nearly 0.2 mm

larger than the via drill diameter) around the vias; the reduced area of exposed copper on

the bottom reduces the amount of solder paste flowing down the vias.

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