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AN1330 Arkusz danych(PDF) 5 Page - STMicroelectronics |
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AN1330 Arkusz danych(HTML) 5 Page - STMicroelectronics |
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5 / 31 page ![]() AN1330 Pin functions 5/31 1 Pin functions 1.1 Pin description 1.2 Block diagram Figure 4. Block diagram Table 1. Pin description N. Name Description 1 OUT Regulator output 2 SYNC Master/slave synchronization. When open, a signal synchronous with the turn-OFF of the internal power is present. When connected to an external signal at a frequency higher than the internal one, then the device is synchronized by the external signal. Connecting the SYNC pins of two devices, the one with the higher frequency works as master and the other one works as slave. 3INH A logical signal (active high) disables the device. With an IHN higher than 2.2 V the device is OFF and with an INH lower than 0.8 V, the device is ON. If INH is not used the pin must be grounded. When it is open, an internal pull-up disables the device. 4 COMP E/A output to be used for frequency compensation 5FB Step-down feedback input. Connecting the output voltage directly to this pin results in an output voltage of 1.235 V. An external resistor divider is required for higher output voltages (the typical value for the resistor connected between this pin and ground is 4.7 k). 6VREF Reference voltage of 3.3 V. No filter capacitor is needed for stability 7 GND Ground 8VCC Unregulated DC input voltage. INHIBIT VOLTAGES MONITOR PEAK TO PEAK CURRENT LIMIT THERMAL SHUTDOWN E/A PWM 1.235V + - - + OSCILLATOR D Ck Q FREQUENCY SHIFTER TRIMMING SUPPLY 1.235V 3.5V DRIVER VREF BUFFER LPDMOS POWER FB SYNC COMP INH VREF GND OUT VCC AM00003v1 |
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