L6206 datasheet(45/53 Pages) STMICROELECTRONICS

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AN1762 APPLICATION NOTE

case the current that can be drawn form the board depends on the supply voltage and on R1 value.

Figure 49 to Figure 51 show the component placement and the two layers layout of the L6206PD Evaluation

Board. A large GND area has been used, to guarantee minimal noise and good power dissipation for the device.

Figure 47. EVAL6206PD.

5.4.1 Important Notes

JP1 : close in INT position for use with PractiSPIN ST7 board

C6, C7 : recommended change to 5.6 nF for safe Overcurrent protection

R2, R3 : recommended change to 100 k for safe Overcurrent protection

R4, R5 : recommended change to 100 k if EN pins are driven from the CN5 connector (for example with Prac-

tiSPIN ST7 board) for safe Overcurrent protection

R16, R22 : set the maximum current obtainable through PractiSPIN (see PractiSPIN documentation)

R1 : recommended change to adequate value (depending on supply voltage) to obtain 5V across D2

JP2, JP3 : close to allow Overcurrent protection

JP4, JP5 : close for on-board OCD threshold adjusting through R6, R7

CN5

: VrefA and VrefB positions are inverted if compared to other EVAL62XX boards.

JP1

R16

R22

JP4

JP5

JP2

JP3

CN5

L6206 Arkusz danych(PDF) 45 Page - STMicroelectronics