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AN2929 Arkusz danych(PDF) 10 Page - STMicroelectronics |
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AN2929 Arkusz danych(HTML) 10 Page - STMicroelectronics |
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10 / 32 page ![]() Testing the board AN2929 10/32 Doc ID 15333 Rev 2 2.2 Precision of the regulation and output voltage ripple The output voltage of the board was measured in different line and load conditions (see Table 4). The output voltage is practically not affected by the line condition. The VDD voltage was also measured to verify that it is inside the operating range of the device. In a dual-output flyback converter, when just one output is regulated, the unregulated output does not rigorously respect the turn ratio. The unregulated output voltage value depends not only on the turn ratio but also, approximately, from the output current ratio (output current of the regulated output divided by the output current of the unregulated output). As confirmed from the results in Table 4, the VDD voltage (unregulated auxiliary output) increases as the load on the regulated output increases. In order to avoid that the VDD voltage exceeds its operating range, an external clamp was used (D6, R19). See schematic in Figure 2. The ripple at the switching frequency superimposed at the output voltage was also measured and the results are given in Table 5. The board is provided with an LC filter for cleaner output voltage. The high-frequency voltage ripple across capacitor C9 (VOUT_FLY), which is the output capacitor of the flyback converter before the LC filter, was also measured to verify the effectiveness of the LC filter and to provide complete results. Table 4. Output voltage and VDD line-load regulation VINAC (V) No load Half load Full load VOUT (V) VDD (v) VOUT (V) VDD (V) VOUT (V) VDD (V) 90 5.05 9.79 5.05 18.9 5.04 19.8 115 5.05 9.71 5.05 18.9 5.04 19.7 230 5.05 9.37 5.05 18.8 5.04 19.6 265 5.05 9.22 5.05 18.8 5.04 19.6 Table 5. Output voltage ripple VINAC (VRMS) Half load Full load VOUT (mV) VOUT_FLY (mV) VOUT (mV) VOUT_FLY (mV) 90 25 275 40 172 115 26 275 37 201 230 26 273 36 194 265 25 272 36 195 |
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