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UPD17P236M4 Arkusz danych(PDF) 20 Page - NEC |
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UPD17P236M4 Arkusz danych(HTML) 20 Page - NEC |
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20 / 32 page ![]() µPD17P236 20 Data Sheet U14776EJ1V0DS00 AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V) Item Symbol Conditions MIN. TYP. MAX. Unit CPU clock cycle time Note tCY1 3.8 33 µs (instruction execution time) tCY2 VDD = 3.0 to 3.6 V 1.9 33 µs INT high/low level width tINTH, tINTL 20 µs RESET low level lwidth tRSL 10 µs Note The CPU clock cycle time (instruction execution time) is determined by the oscillation frequency of the resonator connected and SYSCK (RF: address 02H) of the register file. The figure on the right shows the CPU clock cycle time tCY vs. supply voltage VDD characteristics. tCY vs VDD Supply voltage VDD (V) 2 1 3 4 5 6 7 8 9 10 33 40 2 01 3 4 3.8 1.9 2.2 3.6 Operation guaranteed area |
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