AN2989

Startup sequence

Doc ID 15761 Rev 1

9/28

Note:

The precision of the output data rate is related to the internal oscillator; an error of +/- 10%

should be taken in account.

A typical reading period is defined which is 616 µs shorter than the output data rate period,

in order to prevent the loss of any data produced. During this time period the reading of the

data must be performed and the DataReady signal can be used as a trigger to begin the

reading sequence. At the end of the complete sequence, the DataReady signal goes down

and the rising edge that follows signals that new data are available. If this minimum reading

frequency is not observed, some data loss is possible and the DataReady signal no longer

signifies a trigger signal. The status register can be used to infer whether an overrun has

occurred.

Figure 1.

Reading timing

2.3

DataReady vs. interrupt signal

The device is equipped with two pins that can be activated to generate either the DataReady

or the interrupt signal. The functionality of the pins is selected acting on bit I1(2)_CFGx bits

of the CTRL_REG3 register, according to Table 4 and with the block diagram given in Figure

2.

Table 2.

Output data rate

DR1, DR0

Output data rate

Analog filter

cut-off frequency. (-3 dB)

00

50 Hz

37 Hz

01

100 Hz

74 Hz

10

400 Hz

292 Hz

Table 3.

Timing value to avoid losing data

Time

Description

Min

T0

Data rate

1/ODR

T1

Reading period

T0-T2

T2

New data generation (typ)

616 µs

Table 4.

Data signal on INT 1 and INT 2 pads

I1(2)_CFG1

I1(2)_CFG0

INT 1(2) pin

0

0

Interrupt 1 (2) source

0

1

Interrupt 1 source OR Interrupt 2 source

1

0

DataReady

1

1

Boot running