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AN3065 Arkusz danych(PDF) 5 Page - STMicroelectronics |
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AN3065 Arkusz danych(HTML) 5 Page - STMicroelectronics |
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5 / 33 page ![]() AN3065 Main characteristics and circuit description Doc ID 16279 Rev 2 5/33 1/V2 function necessary to compensate the control loop gain dependence on the mains voltage. Additionally, pin #10 (RUN) is connected to pin# 5 (VFF) through a resistor divider R27 and R32, providing a voltage threshold for brownout protection (AC mains undervoltage). A voltage below 0.8 V shuts down (not latched) the IC and brings its consumption to a considerably lower level. The L6563S restarts as the voltage at the pin rises above 0.88 V. The divider R3, R6, R11 and R15 provides the L6563S pin #7 (PFC_OK) with the information regarding the output voltage level. It is required by the L6563S output voltage monitoring and disables functions used for PFC protection purposes. If the voltage on pin #7 exceeds 2.5 V, the IC stops switching and restarts as the voltage on the pin falls below 2.4 V implementing the so-called dynamic OVP, which prevents an excessive output voltage in case of transients, because of the slow response of the error amplifier. However, if contemporaneously the voltage of the INV pin falls below 1.66 V (typ.), a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling Vcc, bringing its value lower than 6 V before rising up to the turn-on threshold. Additionally If the voltage on pin #7 (PFC_OK) is tied below 0.23 V, the L6563S is shut down. To restart operation of the L6563S the voltage on pin #7 (PFC_OK) has to increase above 0.27 V. This function can be used as a remote on/off control input. To allow interfacing of the board with a D2D converter, the connector J3 allows powering the L6563S with an external Vcc and also manages failure or abnormal conditions via the pins PWM_LATCH and PWM_STOP. The L6563S can be also disabled or enabled to manage properly light load or failure by the D2D via the PFC_OK pin (#7), available at pin #5 of J3 (ON/OFF). For further details please see Section 4.7. |
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