AN3119 datasheet(4/32 Pages) STMICROELECTRONICS

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Main characteristics and circuit description

AN3119

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Doc ID 16849 Rev 2

Main characteristics and circuit description

The main characteristics of the SMPS are:

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Line voltage range: 90 to 265 Vac

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Line frequency (fL): 47 to 63 Hz

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Regulated output voltage: 400 V

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Rated output power: 250 W

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Maximum 2fL output voltage ripple: 20 V pk-pk

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Hold-up time: 10 ms (VDROP after hold-up time: 300 V)

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Minimum switching frequency: 40 kHz

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Minimum estimated efficiency: 93 % (@Vin=90 Vac, Pout=250 W)

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Maximum ambient temperature: 50 °C

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PCB type and size: single side, 35 µm, CEM-1, 88 x 116 mm

This demonstration board implements a power factor correction (PFC) pre-regulator, 250 W

continuous power, delivering a regulated 400 V rail from a wide range mains voltage and

providing for the reduction of the mains harmonics, allowing the European EN61000-3-2 or

the Japanese JEITA-MITI standard to be met. The regulated output voltage is typically the

input for the cascaded isolated DC-DC converter which provides the output rails required by

the load.

The power stage of the PFC is a conventional boost converter, connected to the output of

the D1 rectifier bridge. It is completed by the L2 coil, the D3 diode and the C5 capacitor. The

boost switch is represented by the Q1 and Q2 power MOSFETs, connected in parallel. The

NTC R1 limits the inrush current at switch-on. It has been connected on the DC rail, in

series to the output electrolytic capacitor, in order to improve the efficiency during low-line

operation. In fact the RMS current flowing into the output stage is lower than current flowing

into the input stage at the same input voltage. The board is equipped with an input EMI filter

necessary to filter the switching noise coming from the boost stage.

At startup the L6563S is powered by the capacitor C9 which is charged via the R5 and R11

resistors. The L2 secondary winding and the charge pump circuit (C6, R2, D4 and D5)

generate the Vcc voltage powering the L6563S during normal operations. The L2 secondary

winding is also connected to the L6563S pin #11 (ZCD) through the R14 resistor. Its

purpose is to supply the information that L2 has demagnetized, needed by the internal logic

to trigger a new switching cycle.

The R4, R8, R12, and R15 divider provides, to the L6563S multiplier, the information for the

instantaneous mains voltage which is used to modulate the peak current of the boost.

The R3, R6, R7 with R9 and R10 resistors are dedicated to sensing the output voltage and

giving the feedback information necessary to the L6563S to regulate the output voltage. The

C7, R13 and C10 components are the error amplifier compensation network necessary to

obtain the required loop stability.

The peak current is sensed by the R23 and R24 resistors in series to the MOSFET and the

signal is fed into pin #4 (CS) of the L6563S via the filter by R20 and C14.

C12, R27 and R28 are connected to pin #5 (VFF), they complete an internal peak-holding

circuit which obtains the information on the RMS mains voltage. The voltage signal at this

pin, a DC level equal to the peak voltage on pin #3 (MULT), is fed to a second input to the

multiplier for 1/V2 function necessary to compensate the control loop gain dependence on

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