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UPD17P236M2GT Arkusz danych(PDF) 15 Page - NEC |
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UPD17P236M2GT Arkusz danych(HTML) 15 Page - NEC |
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15 / 32 page ![]() µPD17P236 15 Data Sheet U14776EJ1V0DS00 3.3 Program Memory Reading Procedure (1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the VDD pin. Keep the VPP pin low. (3) Supply 5 V to the VPP pin after waiting for 10 µs. (4) Set the program memory address 0 clear mode by using the mode setting pins. (5) Supply +6 V to VDD and +12.5 V to VPP. (6) Set the program inhibit mode. (7) Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to the CLK pin four times. (8) Set the program inhibit mode. (9) Set the program memory address 0 clear mode. (10) Change the voltage on the VDD and VPP pins to 5 V. (11) Turn off power. The following figure illustrates steps (2) through (9) above. Hi-Z Hi-Z "L" MD3 MD2 MD1 MD0 D0-D7 CLK GND VDD VDD VPP VPP VDD GND VDD+1 Reset Data output Data output One cycle |
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