LTC1642_15 datasheet(9/16 Pages) LINER

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LTC1642

1642fb

APPLICATIO S I FOR ATIO

Hot Circuit Insertion

When a circuit board is inserted into a live backplane its

supply bypass capacitors can draw large currents from the

backplane power bus as they charge. These currents can

permanently damage connector pins and can glitch the

backplane supply, resetting other boards in the system.

The LTC1642 limits the charging currents drawn by a

board’s capacitors, allowing safe insertion into a live

backplane.

In the circuit shown in Figure 1 the LTC1642 and the

external NMOS pass transistor Q1 work together to limit

charging currents. Waveforms at board insertion are

shown in Figure 2. When power is first applied to VCC the

chip holds Q1’s gate at ground. After an adjustable delay

a 25

µA current source begins to charge the external

capacitor C2, so choose C2 to limit the inrush current

IINRUSH charging the board’s bypass capacitance CLOAD

according to the equation:

•

25 A

LOAD

INRUSH

An internal charge pump supplies the 25

µA gate current,

ensuring sufficient gate drive to Q1. At 3V VCCthe minimum

gate drive is 4.5V; at 5V VCCthe minimum is 10V; at 15V VCC

the minimum is again 4.5V, due to an internal zener clamp

from the GATE pin to ground. Resistor R3 limits this zener’s

transient current during board insertion and removal and

protects against high frequency oscillations in Q1. D1

provides additional protection against supply spikes.

The delay before the GATE pin voltage begins ramping is

determined by the system timer. It comprises an external

capacitor C1 from the RST TMR pin to ground; an internal

µAcurrentsourcefeedingRSTTMRfromVCC;aninternal

comparator, with the noninverting input tied to RST TMR

and the inverting input tied to the 1.22V reference; and an

internal NMOS pull-down. In standby, the NMOS holds

RST TMR at ground. When the timer starts the NMOS

turns off and the RST TMR voltage ramps up as the current

source charges the capacitor. When RST TMR reaches

1.22V the timer comparator trips, the GATE voltage begins

ramping up and RST TMR returns to ground. The timer

delay is:

tRSTTMR = (615ms/µF) C1.

The second RST TMR cycle indicates that VOUT is within

tolerance; it is discussed in the Undervoltage Monitor

section.

GATE

SENSE

FAULT

BRK TMR

VCC

0.010

Ω

FDS6630A

GND

LTC1642

RST TMR

1642 F01

100

Ω

330

Ω

1N4705

18V

0.047

µF

CLOAD

0.33

µF

0.33

µF

ALL RESISTORS

±5% UNLESS NOTED

RESET DELAY = 200ms

SHORT-CIRCUIT DURATION = 10ms

VIN

12V

2.5A

VOUT

24k

R10

30k

Figure 1. Supply Control Circuitry

Powering-Up in Current Limit

Ramping the GATE pin voltage limits the current to I =

µA • CLOAD/C2, where C2 is the external capacitor

connected to the GATE and CLOAD is the load capacitance.

If the value of CLOAD is uncertain, then a worst-case design

can often result in needlessly long ramp times, and it may

be better to limit the charging current by powering up in

current limit.

Current Limiting and Solid-State Circuit Breaker

The current can be limited by connecting a sense resistor

between the LTC1642’s VCC and SENSE pins. When the

voltage drop across this resistor reaches a limiting value,

Figure 2. Timing at Board Insertion

100ms/DIV

1642 F02

10V/DIV

RST TMR

2V/DIV

GATE

20V/DIV

VOUT

20V/DIV

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