AN1709 datasheet(21/38 Pages) STMICROELECTRONICS

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EMC DESIGN GUIDE FOR ST MICROCONTROLLERS

3.1.3 I/O Features & properties

Although integrated circuit data sheets provide the user with conservative limits and condi-

tions in order to prevent damage, sometimes it is useful for the hardware system designer to

know the internal failure mechanisms: the risk of exposure to illegal voltages and conditions

can be reduced by smart protection design.

It is not possible to classify and to predict all the possible damage resulting from violating max-

imum ratings and conditions, due to the large number of variables that come into play in de-

fining the failures: in fact, when an overvoltage condition is applied, the effects on the device

can vary significantly depending on lot-to-lot process variations, operating temperature, ex-

ternal interfacing of the Microcontroller with other devices, etc.

In the following sections, background technical information is given in order to help system de-

signers to reduce risk of damage to the Microcontroller device.

3.1.3.1 Electrostatic Discharge and Latch-up

CMOS integrated circuits are generally sensitive to exposure to high voltage static electricity,

which can induce permanent damage to the device: a typical failure is the breakdown of thin

oxides, which causes high leakage current and sometimes shorts.

Latch-up is another typical phenomenon occurring in integrated circuits: unwanted turning on

of parasitic bipolar structures, or silicon-controlled rectifiers (SCR), may overheat and rapidly

destroy the device. These unintentional structures are composed of P and N regions which

work as emitters, bases and collectors of parasitic bipolar transistors: the bulk resistance of

the silicon in the wells and substrate act as resistors on the SCR structure. Applying voltages

below VSS or above VDD, and when the level of current is able to generate a voltage drop

across the SCR parasitic resistor, the SCR may be turned on; to turn off the SCR it is neces-

sary to remove the power supply from the device.

ST Microcontroller design implements layout and process solutions to decrease the effects of

electrostatic discharges (ESD) and latch-up. Of course it is not possible to test all devices, due

to the destructive nature of the mechanism; in order to guarantee product reliability, destruc-

tive tests are carried out on groups of devices, according to STMicroelectronics internal

Quality Assurance standards and recommendations (see 2.1.2 Latch-Up (LU)).

AN1709 Arkusz danych(PDF) 21 Page - STMicroelectronics