AN2715

DDR IBIS model selection

Doc ID 14454 Rev 1

7/12

The correlation between bits 0-8 (or 0-7) of the model group names and the bits of each

register is given below:

●

Register SSTLPAD_CFG_CTR (Address 0xFCA800F0).

b7 = SSTLPAD_CFG_CTR [15] = dram_type (1 = DDR2 interface)

b6 = SSTLPAD_CFG_CTR [3] = drive_mode_s_w (1 = Weak drive strength)

b5 = SSTLPAD_CFG_CTR [2] = prog_a (slope of the signals. 00 = slower slope)

b4 = SSTLPAD_CFG_CTR [1] = prog_b (slope of the signals. 11 = higher slope)

b3 = Internal level forced to zero.

b2 = Two cases:

–

Internal level forced to zero for CLKP or CLKN signals.

–

SSTLPAD_CFG_CTR [12] = pseudo_dif_

This is the bit register value for the signals DQS & nDQS (0 = diff. sig.).

●

Register MEM11_CTL [1:0] (Address 0xFC60002C) = rtt_pad_terminat[1:0].

The following table is for the DQS, nDQS and DQ signals only. For all the other signals

b1 = b0 = 0 (no ODT).

Note:

“-“ means “don’t care”.

5.1

Example

The setting of the registers SSTLPAD_CFG_CTR and MEM11_CTL is normally done at

each system boot-up by the XLOADER part of the boot code.

Let’s assume, as an example, that at the end of the boot operation the application reads

these two registers and finds the following values:

●

Register SSTLPAD_CFG_CTR (Address 0xFCA800F0) = 0x0000EAAD.

●

Register MEM11_CTL Register (Address 0xFC60002C) = 0x03000002.

The correct model to be selected from the library with the above values is the following:

Table 6.

DQS, nDQS and DQ on die termination (ODT)

MEM11_CTL [1]

MEM11_CTL [0]

B1

B0

Description

00

0

-

ODT disabled

0

1

1

1

ODT= 75 Ohm

1

0

1

0

ODT = 150 Ohm

11

Reserved

Table 7.

Example of relation between DDR block signals and the used model

DDR block signal name

IBIS model used for application board

DDR_CLKP & DDR_CLKN

DDR_DIFF_[b7:b0] = DDR_DIFF_11100000

DDR_DQS_0 & nDDR_DQS_0

DDR_DQS_1 & nDDR_DQS_1

If READ => DDR_DIFF_[b7:b0] = DDR_DIFF_11100010

If WRITE => DDR_DIFF_[b7:b0] = DDR_DIFF_11100000