UPD703003A datasheet(21/40 Pages) NEC

21 / 40 page

µPD703003A, 703004A, 703025A

Data Sheet U13188EJ4V0DS00

(1) Clock timing

Parameter

Symbol

Conditions

25 MHz Version

33 MHz Version

Unit

MIN.

MAX.

MIN.

MAX.

X1 input cycle

<1>

tCYX

Direct mode

Note 1

PLL mode (PLL locked)

200

Note 1

151

Note 1

X1 input high-level width

<2>

tWXH

Direct mode

X1 input fall time

<5>

tXF

Direct mode

PLL mode

CPU operating frequency

–

Note 2

MHz

Notes 1. When using A/D converter: 100 ns

When not using A/D converter: 250 ns

2. When using A/D converter: 5 MHz

When not using A/D converter: 2 MHz

3. When using A/D converter: 200 ns

When not using A/D converter: 500 ns

Remark

T = tCYK

PLL mode

X1 input low-level width

<3>

tWXL

Direct mode

PLL mode

X1 input rise time

<4>

tXR

Direct mode

CLKOUT output cycle

<6>

tCYK

Note 3

CLKOUT input high-level width

<7>

tWKH

0.5T – 5

CLKOUT input low-level width

<8>

tWKL

0.5T – 5

CLKOUT input rise time

<9>

tKR

CLKOUT input fall time

<10> tKF

Delay time from X1

↓ to CLKOUT <11> tDXK

Direct mode

PLL mode

X1 (input)

CLKOUT (output)

<1>

<2>

<4>

<5>

<6>

<7>

<11>

<8>

<9>

<10>

<3>

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