UPD703003GC datasheet(56/82 Pages) NEC

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µPD703003

Data Sheet U12261EJ2V1DS00

DC Characteristics (TA = –40 to +85

°C, VDD = 5.0 V ±10%, VSS = 0 V)

(1/2)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Units

High-level input voltage

VIH

Except for X1 and pins listed in Note

2.2

VDD + 0.3

Note

0.8 VDD

VDD + 0.3

Low-level input voltage

VIL

Except for X1 and pins listed in Note

–0.5

+0.8

Note

–0.5

0.2 VDD

High-level clock input voltage

VXH

0.8 VDD

VDD + 0.5

Low-level clock input voltage

VXL

–0.5

+0.6

Schmitt trigger input

VT+

Note, rising edge

3.0

Threshold voltage

VT–

Note, falling edge

2.0

Schmitt trigger input hysteresis width

VT+ – VT–

Note

0.5

High-level output voltage

VOH

IOH = –2.5 mA

0.7 VDD

IOH = –100

µAVDD – 0.5

Low-level output voltage

VOL

IOL = 2.5 mA

0.45

High-level input leak current

ILIH

VI = VDD

µA

Low-level input leak current

ILIL

VI = 0 V

–10

µA

High-level output leak current

ILOH

VO = VDD

µA

Low-level output leak current

ILOL

VO = 0 V

–10

µA

Software pull-up resistance

P35/INTP131/SO3,

Ω

P36/INTP132/SI3,

P37/INTP133/SCK3

Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/

INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,

P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/

SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE

Remarks 1. TYP. values are reference values for when TA = 25

°C and VDD = 5.0 V.

φ = Internal system clock frequency

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