AN3117 datasheet(7/28 Pages) STMICROELECTRONICS

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AN3117

DMA controller description

Doc ID 16846 Rev 4

7/28

1.2

Peripherals supported by DMA

The different peripherals supporting DMA transfers are listed in Table 2 and Table 3. The

peripherals served by the DMA and the bus system structure are represented in Figure 1.

Note:

ADC1 can be mapped on each of the four channels: depending on the

SYSCFG_RMPCR1[1:0] bits (please refer to the ADC chapter and the SYSCFG registers

chapter in the RM0031 reference manual). The default mapping is Channel 0.

TIM4 can be mapped on each of the four channels: depending on the

SYSCFG_RMPCR1[3:2] bits (please refer to the Timer chapter and the SYSCFG registers

chapter in the RM0031 reference manual). The default mapping is Channel 3.

DAC is not present in STM8L05xxx devices.

Table 2.

Peripherals served by DMA and channel allocations (medium+ and high

density devices)

Peripheral

DMA Ch.0

request source

DMA Ch.1

request source

DMA Ch.2 request

source

DMA Ch.3 request

source

ADC1 (1)

EOC

SPI1

SPI1_RX

SPI1_TX

I2C

I2C_RX

I2C_TX

USART1

USART1_TX

USART1_RX

DAC

DAC_CH2TRIG

(Note 3)

DAC_CH1TRIG

(Note 3)

TIM2

TIM2_CC1

TIM2_U

TIM2_CC2

TIM3

TIM3_U

TIM2_CC1

TIM3_CC2

TIM1

TIM1_CC3

TIM1_CC4

TIM1_U

TIM1_CC1

TIM1_COM

TIM1_CC2

USART2

USART2_TX

USART2_RX

USART3

USART3_TX

USART3_RX

SPI2

SPI2_RX

SPI2_TX

TIM5

TIM5_U

TIM5_CC1

TIM5_CC2

AES

AES_IN

AES_OUT

TIM4(2)

TIM4_U

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