Doc ID16895 Rev 2

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AN3126

DAC main features

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1.2

Data format

The DAC accepts data in 3 integer formats: 8-bit, 12-bit right aligned and 12-bit left aligned.

A 12-bit value can range from 0x000 to 0xFFF, with 0x000 being the lowest and 0xFFF

being the highest value.

Figure 1. DAC data format

1.3

Dual channel mode

Note:

This feature is supported only for products that embed at least 2 DACs.

The DAC has two output channels, each with its own converter. In dual DAC channel mode,

conversions could be done independently or simultaneously.

When the DAC channels are triggered by the same source, both channels are grouped

together for synchronous update operations and conversions are done simultaneously.

1.4

Dedicated timers

In addition to the software and External triggers, the DAC conversion can be triggered by

different timers.

TIM6 and TIM7 are basic timers and are basically designed for DAC triggering.

Each time a DAC interface detects a rising edge on the selected Timer Trigger Output

(TIMx_TRGO), the last data stored in the DAC_DHRx register is transferred to the

DAC_DORx register (an example for STM32F100x is given in Figure 2).

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