PM0075 datasheet(12/31 Pages) STMICROELECTRONICS

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Reading/programming the embedded Flash memory

PM0075

12/31

Doc ID 17863 Rev 2

In case of non-availability of a high frequency clock in the system, Flash memory accesses

can be made on a half cycle of HCLK (AHB clock), the frequency of HCLK permitting (half-

cycle access can only be used with a low-frequency clock of less than 8 MHz that can be

obtained with the use of HSI or HSE but not of PLL). This mode can be chosen by setting a

control bit in the Flash access control register.

Note:

Half-cycle access cannot be used when there is a prescaler different from 1 on the AHB

clock.

Access time tuner

In order to maintain the control signals to read the Flash memory, the ratio of the prefetch

controller clock period to the access time of the Flash memory has to be programmed in the

Flash access control register. This value gives the number of cycles needed to maintain the

control signals of the Flash memory and correctly read the required data. After reset, the

value is zero and only one cycle is required to access the Flash memory.

2.2.2

D-Code interface

The D-Code interface consists of a simple AHB interface on the CPU side and a request

generator to the Arbiter of the Flash access controller. D-code accesses have priority over

prefetch accesses. This interface uses the Access Time Tuner block of the prefetch buffer.

2.2.3

Flash access controller

Mainly, this block is a simple arbiter between the read requests of the prefetch/I-code and D-

Code interfaces.

D-Code interface requests have priority over I-Code requests.

2.3

Flash program and erase controller (FPEC)

The FPEC block handles the program and erase operations of the Flash memory. The

FPEC consists of seven 32-bit registers.

●

FPEC key register (FLASH_KEYR)

●

Option byte key register (FLASH_OPTKEYR)

●

Flash control register (FLASH_CR)

●

Flash status register (FLASH_SR)

●

Flash address register (FLASH_AR)

●

Option byte register (FLASH_OBR)

●

Write protection register (FLASH_WRPR)

An ongoing Flash memory operation will not block the CPU as long as the CPU does not

access the Flash memory.

2.3.1

Key values

The key values are as follows:

●

RDPRT key = 0x00A5

●

KEY1 = 0x45670123

●

KEY2 = 0xCDEF89AB

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