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LT1339

APPLICATIONS INFORMATION

switch gates load the driver outputs such that rise/fall

times exceed about 100ns, buffers can sometimes result

in efficiency gains. Buffers also reduce the effect of back

injection into the bottom side driver output due to coupling

of switch node transitions through the switch FET CMILLER.

Paying the Physicists

In high power synchronous buck configurations, certain

physical characteristics of the external MOSFET switches

can impact conversion efficiency. As the input voltage

approaches about 30V, the bottom MOSFETs will begin to

exhibit “phantom turn-on.” This phenomenon is caused

by coupling of the instantaneous voltage step on the

bottom side switch drain through CMILLER to the device

gate, yielding internal localized gate-source voltages above

the turn-on threshold of the FET. This generates a shoot-

through blip that ultimately eats away at efficiency num-

bers. In Figure 8 a negative prebias circuit is added to the

bottom side gate. The addition of this

∼3V of negative

offset to the bottom gate drive provides additional off-

state voltage range to prevent phantom turn-on.

This type of prebias circuit is used in the 48V to 5V, 50A

converter pictured in the Typical Applications section.

As currents increase beyond the 10A to 15A range, the

bottom side FET body diode experiences hard turn-on

during switch dead time due to local current loop induc-

tance preventing the timely transfer of charge to the

Schottky catch diode. The charge current required to

commutate this body diode creates a high dV/dt Schottky

avalanche when the diode charge is finally exhausted (due

to an effective inductor current discontinuity at the

moment the body diode no longer requires charge). This

generates an increased turn-on power burst in the topside

switch, causing additional conversion efficiency loss. This

effect of this parasitic inductance can be reduced by using

FETKEY

TM MOSFETs, which have parallel catch Schottky

diodes internal to their packages.

FETKEY MOSFETs are

FETKEY is a trademark of International Rectifier Corporation.

12VIN

PGND

LT1339

ZTX649

ZTX749

D1N914

1339 F08

10k

µF

3.3V

Figure 8. Bottom Side Driver Negative Prebias Circuit

not available for high voltages, so as input voltage contin-

ues to increase, they can no longer be used. Because this

necessitates the use of discrete FETs and Schottkys,

interdigitation of a number of smaller devices is required

to minimize parasitic inductances. This technique is also

used in the 48V to 5V, 50A converter shown in the Typical

Applications section.

Optimizing Transient Response—Compensation

Component Values

The dominant compensation point for an LT1339 con-

verter is the VC pin (Pin 7), or error amplifier output. This

pin is connected to a series RC network, RVC and CVC. The

infinite permutations of input/output filtering, capacitor

ESR, input voltage, load current, etc. make for an empirical

method of optimizing loop response for a specific set of

conditions.

Loop response can be observed by injecting a step change

in load current. This can be achieved by using a switchable

load. With the load switching, the transient response of the

output voltage can be observed with an oscilloscope.

Iterating through RC combinations will yield optimized

response. Refer to LTC Application Note 19 in

1990 Linear

Applications Handbook, Volume 1 for more information.

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