LTC1096LCS8 datasheet(4/8 Pages) LINER

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LTC1096L/LTC1098L

AC CHARACTERISTICS

VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

tSMPL

Analog Input Sample Time

See Operating Sequences

1.5

CLK Cycles

fSMPL(MAX) Maximum Sampling Frequency

16.5

kHz

tCONV

Conversion Time

See Operating Sequences

CLK Cycles

tdDO

Delay Time, CLK

↓ to DOUT Data Valid

See Test Circuits

500

1000

tdis

Delay Time, CS

↑ to DOUT Hi-Z

See Test Circuits

220

800

ten

Delay Time, CLK

↓ to DOUT Enable

See Test Circuits

160

480

thDO

Time Output Data Remains Valid After CLK

↓

CLOAD = 100pF

400

DOUT Fall Time

See Test Circuits

250

DOUT Rise Time

See Test Circuits

200

CIN

Input Capacitance

Analog Inputs

On Channel

Off Channel

Digital Input

LTC1096L

CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1096L. A logic high on this input

disables the LTC1096L and disconnects the power to the

LTC1096L.

IN+ (Pin 2): Analog Input. This input must be free of noise

with respect to GND.

IN– (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

VREF (Pin 5): Reference Input. The reference input defines

the span of the A/D converter and must be kept free of

noise with respect to GND.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the serial

data transfer.

VCC (Pin 8): Power Supply Voltage. This pin provides

power to the A/D converter. It must be free of noise and

ripple by bypassing directly to the analog ground plane.

LTC1098L

CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1098L. A logic high on this input

disables the LTC1098L and disconnects the power to the

LTC1098L.

CHO (Pin 2): Analog Input. This input must be free of noise

with respect to GND.

The q denotes specifications which apply over the full operating

temperature range.

Note 1: Absolute Maximum Ratings are those values beyond which the life

of a device may be impaired.

Note 2: All voltage values are with respect to GND.

Note 3: This device is specified at 2.65V. Consult factory for 5V specified

devices.

Note 4: Linearity error is specified between the actual end points of the

A/D transfer curve.

Note 5: Total unadjusted error includes offset, full scale, linearity,

multiplexer and hold step errors.

Note 6: Two on-chip diodes are tied to each reference and analog input

which will conduct for reference or analog input voltages one diode drop

below GND or one diode drop above VCC. This spec allows 50mV forward

bias of either diode for 2.65V

≤ VCC ≤ 3.6V. This means that as long as the

reference or analog input does not exceed the supply voltage by more than

50mV, the output code will be correct. To achieve an absolute 0V to 3V

input voltage range will therefore require a minimum supply voltage of

2.950V over initial tolerance, temperature variations and loading.

Note 7: Channel leakage current is measured after the channel selection.

PI FU CTIO S

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