LTC1531CSW datasheet(6/16 Pages) LINER

6 / 16 page

LTC1531

APPLICATIONS INFORMATION

The LTC1531 is an isolated self-powered dual differential

comparator. It contains a switched-capacitor comparator

that is self-powered through a capacitive isolation barrier.

The capacitive isolation barrier provides 2500VRMS of

isolation. The isolated comparator cycles between storing

power and performing sampled comparisons. During the

power delivery cycle, the nonisolated powered side deliv-

ers power through the internal isolation capacitors and

rectifier onto an external storage capacitor. Periodically

the isolated comparator makes a comparison if sufficient

voltage has been stored on the external supply capacitor.

See Timing and Block Diagrams.

During a comparison, the isolated side uses the energy

stored on the external capacitor to deliver a regulated 2.5V

power source for 108

µs followed by a sampled compari-

son. The result is transmitted back to the nonisolated

powered side and latched as the logic level DATA output.

A comparison will occur during the listen cycle if sufficient

voltage (3.3V) has been stored on the isolated external

capacitor. New DATA is latched only if a comparison was

actually done. A zero-crossing trigger pulse output for

firing a triac, ZCDATA, is available to trigger a triac when

the latched DATA output is high. A VALID data output pulse

is provided after each power-listen cycle in which a com-

parison was done to indicate that DATA has been updated.

The VALID output can be used to clock external circuitry

when a new comparator DATA value occurs.

POWER-LISTEN CYCLE

Self-Powering Through the Isolation Barrier

The LTC1531 comparator powered side toggles between

delivering power to the isolated side and listening for a

comparison result (see Timing Diagram). During the power

cycle, AC power is delivered through the isolation capaci-

tors, formed in the lead frame, to the isolated side. During

the listen cycle, the powered side receives pulses from the

isolated side and determines if a valid comparison

occurred.

The isolated side of the LTC1531 requires an external

capacitor connected to VPW whose value must be large

enough to sustain less than a 300mV drop for 108

µs with

the internal + external VREG load current. Power is deliv-

ered to this external capacitor through the internal isola-

tion capacitors and rectifiers during the power cycle.

When this voltage reaches approximately 3.3V, the com-

pare circuitry is enabled and a comparison will occur

during the next listen cycle. With VCC = 5V, this capacitive

coupled isolated power source can be modeled as an

equivalent 5.3V to 6.5V source with a 100k

Ω source

impedance. The VPW pin will tend to self-regulate at 3.3V

with a ripple determined by the discharge current supplied

during the 108

µs VREG output pulse and the external

capacitor value. The value of the capacitor affects the initial

start-up time and the ripple voltage on VPW, but it does not

influence the sample rate of the comparator. This is

because the sample rate is determined by the rate of power

delivered through the isolation barrier and the rate it is

consumed in the internal plus external isolated circuits.

Any excessive external DC loading on VPW may prevent the

capacitor voltage from reaching the required 3.3V enable

voltage. Up to 20

µA of continuous loading on VPW can be

tolerated based on the 100k, 5.3V model of the power

source (see Typical Applications for examples). The qui-

escent current of the isolated side is approximately 2

µA

to 3

µA.

SAMPLE RATE

The comparator sample rate depends on the charging rate

through the isolated capacitors and the external + internal

load current . The power-listen cycles at 700Hz to 900Hz,

however, a comparison will only occur when VPW exceeds

the 3.3V enable voltage. Typical sample rate for light

loading is 200Hz to 300Hz. The actual sampling is not

uniform, but occurs during the listen period of the power

cycle and when VPW ≥ 3.3V. Typical sample rates for

various supply and load conditions are plotted in Figure 3.

Continuous micropower loads will also decrease the sample

rate.

VREG Reference Output

The VREG reference output pulses on for approximately

108

µs at 2.5V. During the off time, VREG does not go high

impedance. The VREG output stage is shown in Figure 5.

Large capacitance should not be attached to VREG in order

to avoid power loss. Charging of the VREG output capaci-

LTC1531CSW Arkusz danych(PDF) 6 Page - Linear Technology

LTC1531CSW Arkusz danych(HTML) 6 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Arkusz danych Pobierz

Link URL